Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

ABSTRACT

A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial carrier is removed. A backside interconnect structure has a first conductive layer formed over the molding compound to electrically connect to the contact pads. A first insulating layer is formed over the first conductive layer. A portion of the first insulating layer is removed to expose the first conductive layer. Solder material is deposited in electrical contact with the first conductive layer. The solder material is reflowed to form a solder bump. A wire bond electrically connects to a contact pad. A front-side interconnect structure can be formed through the molding compound to the contact pads.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to a semiconductor device and method of forming thedevice using a sacrificial carrier.

BACKGROUND OF THE INVENTION

Semiconductor devices are found in many products in the fields ofentertainment, communications, networks, computers, and householdmarkets. Semiconductor devices are also found in military, aviation,automotive, industrial controllers, and office equipment. Thesemiconductor devices perform a variety of electrical functionsnecessary for each of these applications.

The manufacture of semiconductor devices involves formation of a waferhaving a plurality of die. Each semiconductor die contains hundreds orthousands of transistors and other active and passive devices performinga variety of electrical functions. For a given wafer, each die from thewafer typically performs the same electrical function. Front-endmanufacturing generally refers to formation of the semiconductor deviceson the wafer. The finished wafer has an active side containing thetransistors and other active and passive components. Back-endmanufacturing refers to cutting or singulating the finished wafer intothe individual die and then packaging the die for structural support andenvironmental isolation.

One goal of semiconductor manufacturing is to produce a package suitablefor faster, reliable, smaller, and higher-density integrated circuits(IC) at lower cost. Flip chip packages or wafer level chip scalepackages (WLCSP) are ideally suited for ICs demanding high speed, highdensity, and greater pin count. Flip chip style packaging involvesmounting the active side of the die facedown toward a chip carriersubstrate or printed circuit board (PCB). The electrical and mechanicalinterconnect between the active devices on the die and conduction trackson the carrier substrate is achieved through a solder bump structurecomprising a large number of conductive solder bumps or balls. Thesolder bumps are formed by a reflow process applied to solder materialdeposited on contact pads which are disposed on the semiconductorsubstrate. The solder bumps are then soldered to the carrier substrate.The flip chip semiconductor package provides a short electricalconduction path from the active devices on the die to the carriersubstrate in order to reduce signal propagation, lower capacitance, andachieve overall better circuit performance.

In many applications, it is desirable to stack WLCSPs. Appropriateelectrical interconnect must be provided for complete deviceintegration. The interconnect typically involves formation ofredistribution layers (RDL) and other conductive lines and tracks. Thesemetal lines have limited pitch and line spacing due to etchingprocessing. The formation of the interconnect structure requires a highdegree of alignment accuracy in attaching the die to the wafer carrierfor subsequent encapsulation and further RDL buildup processes.

A need exists to form the interconnect structures for WLCSPs whileaccounting for the interconnect alignment requirements.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a method of making asemiconductor device comprising the steps of providing a sacrificialcarrier, forming a plurality of contact pads on the sacrificial carrier,mounting a first semiconductor die to electrically connect to thecontact pads, encapsulating the first semiconductor die with moldingcompound, removing the sacrificial carrier, forming a first conductivelayer over the molding compound in electrical contact with the contactpads, forming a first insulating layer over the first conductive layer,removing a portion of the first insulating layer to expose the firstconductive layer, depositing solder material in electrical contact withthe first conductive layer, and reflowing the solder material to form asolder bump.

In another embodiment, the present invention is a method of making asemiconductor device comprising the steps of providing a sacrificialcarrier, forming a plurality of contact pads on the sacrificial carrier,mounting a first semiconductor die to electrically connect to thecontact pads, encapsulating the first semiconductor die with moldingcompound, forming a first conductive layer over the molding compound inelectrical contact with the contact pads, forming a first insulatinglayer over the first conductive layer, and removing a portion of thefirst insulating layer to expose the first conductive layer.

In another embodiment, the present invention is a method of making asemiconductor package comprising the steps of providing a sacrificialcarrier, forming a plurality of contact pads on the sacrificial carrier,mounting a first semiconductor die to electrically connect to thecontact pads, encapsulating the first semiconductor die with moldingcompound, and forming an interconnect structure over the moldingcompound in electrical contact with the contact pads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flip chip semiconductor device with solder bumps providingelectrical interconnect between an active area of the die and a chipcarrier substrate;

FIGS. 2 a-2 f illustrate formation of a semiconductor package using asacrificial carrier;

FIG. 3 illustrates the semiconductor package with solder bumps and wirebonds;

FIGS. 4 a-4 c illustrate an alternate formation of the semiconductorpackage with a sacrificial carrier;

FIG. 5 illustrates the semiconductor package with wire bondinterconnects to the semiconductor die;

FIGS. 6 a-6 b illustrate the semiconductor package with front-side andbackside interconnects;

FIG. 7 illustrates the semiconductor package with pillars under thecontact pads;

FIG. 8 illustrates the semiconductor package with solder bump and wirebond interconnects to the die;

FIG. 9 illustrates the semiconductor package with underfill materialdisposed under the semiconductor die;

FIG. 10 illustrates the semiconductor package with secondary die mountedto the front-side interconnects;

FIG. 11 illustrates the semiconductor package with the sacrificialcarrier left intact for heat dissipation; and

FIG. 12 illustrates the semiconductor package with photoresist leftintact between the contact pads.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the Figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

The manufacture of semiconductor devices involves formation of a waferhaving a plurality of die. Each die contains hundreds or thousands oftransistors and other active and passive devices performing one or moreelectrical functions. For a given wafer, each die from the wafertypically performs the same electrical function. Front-end manufacturinggenerally refers to formation of the semiconductor devices on the wafer.The finished wafer has an active side containing the transistors andother active and passive components. Back-end manufacturing refers tocutting or singulating the finished wafer into the individual die andthen packaging the die for structural support and/or environmentalisolation.

A semiconductor wafer generally includes an active surface havingsemiconductor devices disposed thereon, and a backside surface formedwith bulk semiconductor material, e.g., silicon. The active side surfacecontains a plurality of semiconductor die. The active surface is formedby a variety of semiconductor processes, including layering, patterning,doping, and heat treatment. In the layering process, semiconductormaterials are grown or deposited on the substrate by techniquesinvolving thermal oxidation, nitridation, chemical vapor deposition,evaporation, and sputtering. Photolithography involves the masking ofareas of the surface and etching away undesired material to formspecific structures. The doping process injects concentrations of dopantmaterial by thermal diffusion or ion implantation.

Flip chip semiconductor packages and wafer level packages (WLP) arecommonly used with integrated circuits (ICs) demanding high speed, highdensity, and greater pin count. Flip chip style semiconductor device 10involves mounting an active area 12 of die 14 facedown toward a chipcarrier substrate or printed circuit board (PCB) 16, as shown in FIG. 1.Active area 12 contains active and passive devices, conductive layers,and dielectric layers according to the electrical design of the die.Analog circuits may be created by the combination of one or more passivedevice formed within active area 12 and may be electricallyinterconnected. For example, an analog circuit may include one or moreinductor, capacitor and resistor formed within active area 12. Theelectrical and mechanical interconnect is achieved through a solder bumpstructure 20 comprising a large number of individual conductive solderbumps or balls 22. The solder bumps are formed on bump pads orinterconnect sites 24, which are disposed on active area 12. The bumppads 24 connect to the active circuits by conduction tracks in activearea 12. The solder bumps 22 are electrically and mechanically connectedto contact pads or interconnect sites 26 on carrier substrate 16 by asolder reflow process. The flip chip semiconductor device provides ashort electrical conduction path from the active devices on die 14 toconduction tracks on carrier substrate 16 in order to reduce signalpropagation, lower capacitance, and achieve overall better circuitperformance.

Further detail of forming a semiconductor package in accordance withsemiconductor device 10 is shown in FIGS. 2 a-2 f. In FIG. 2 a, a dummyor sacrificial metal carrier 30 is shown. Metal carrier 30 is made withcopper (Cu), aluminum (Al), or other stiff material. Carrier 30 can alsobe flexible tape. A photoresist layer 32 is deposited on metal carrier30. A plurality of openings is formed by a photo patterning process todefine areas for selective plating. Contact pads 34 are then selectivelyplated on photoresist defined opening areas. Contact pads 34 can be madewith Cu, tin (Sn), nickel (Ni), gold (Au), or silver (Ag). Metal carrier30 serves as a support member and plating current path for theelectroplating process to form wettable metal contact pads 34 on themetal carrier. Part or all of photoresist 32 is removed by a resiststripper. Alternatively, a layer of photoresist 32 may remain betweencontact pads 34.

In FIG. 2 b, semiconductor die 36 and 40 are mounted to contact pads 34on metal carrier 30 with solder bumps 38 and 42, respectively.Alternatively, discrete components or other semiconductor packages canbe mounted to contact pads 34. An optional underfill material can beformed below semiconductor die 36 and 40. A molding compound 44 isformed around semiconductor die 36 and 40 to encapsulate the die,interconnections, and contact pads. The metal carrier is removed by anetching process to expose contact pads 34 as shown in FIG. 2 c.

In FIG. 2 d, the semiconductor die are inverted such that contact pads34 face upward. An optional process carrier 50 is mounted to a backsideof the semiconductor die using adhesive layer 48 to support the package.The adhesive layer can be made with thermally or ultraviolet (UV) lightreleasable temporary adhesive, typically having a glass transitiontemperature (Tg) of at least 150° C. A conductive layer 46 is sputteredand patterned, or selectively plated, on a surface of molded compound 44using an adhesion layer, such as titanium (Ti). Conductive layer 46 ismade with Cu, Al, Au, or alloys thereof. Conductive layer 46electrically connects to contact pads 34 according to the electricalfunction and interconnect requirements of semiconductor die 36 and 40.

In FIG. 2 e, an insulating layer 51 is formed over molding compound 44and conductive layer 46. The insulating layer 51 can be made with singleor multiple layers of photosensitive polymer material or otherdielectric material having low cure temperature, e.g. less than 200° C.A portion of insulating layer 51 is removed by an etching process, suchas photo patterning or chemical etching, to form openings and exposeconductive layer 46. A conductive layer 52 is formed over insulatinglayer 51 to electrically contact conductive layer 46. An insulatinglayer 54 is formed over conductive layer 52 and insulating layer 51. Theinsulating layer 54 can be made with single or multiple layers ofphotosensitive polymer material or other dielectric material having lowcure temperature, e.g. less than 200° C. A portion of insulating layer54 is removed by an etching process, such as photo patterning orchemical etching, to form openings and expose conductive layer 52.Conductive layers 46 and 52 and insulating layers 51 and 54 constitute aportion of an interconnect structure which routes electrical signalsbetween semiconductor die 36 and 40, as well as external to the package.Additional insulating layers and conductive layers can be used in theinterconnect structure.

In FIG. 2 f, an electrically conductive solder material is depositedover conductive layer 52 through an evaporation, electrolytic plating,electroless plating, ball drop, or screen printing process. The soldermaterial can be any metal or electrically conductive material, e.g., Sn,lead (Pb), Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof. Thesolder material is reflowed by heating the conductive material above itsmelting point to form spherical balls or bumps 56. In some applications,solder bumps 56 are reflowed a second time to improve electrical contactto conductive layer 52. An additional under bump metallization canoptionally be formed under solder bumps 56. The interconnections can besolder bumps or bond wires.

Process carrier 50 and adhesive layer 48 are removed. Alternatively,process carrier 50 and adhesive layer 48 can remain attached to thesemiconductor device and operate as a heat sink for thermal dissipationor electromagnetic interference (EMI) barrier.

FIG. 3 illustrates the semiconductor device from FIGS. 2 a-2 f withsemiconductor device 58 electrically connected to solder bumps 56. Inaddition, wire bonds 60 are electrically connected to conductive layer52. Bond wires 62 extend from wire bonds 60 to other semiconductordevices or external electrical connections. Solder bumps 56 and bondwires 62 provide electrical interconnect for semiconductor die 36 and40.

Another embodiment of the initial stages of making the semiconductordevice is shown in FIGS. 4 a-4 c. In FIG. 4 a, a dummy or sacrificialmetal carrier 70 is shown. Metal carrier or foil 70 can be circular orrectangular and made with Cu or Al. A process carrier 72 is mounted tocarrier 70 with adhesive layer 74. A photoresist layer 76 is depositedon metal carrier 70. A plurality of openings is formed by a photopatterning process to define areas for selective plating. Contact pads78 are then selectively plated on photoresist defined opening areas.Contact pads 78 can be made with Cu, Sn, Ni, Au, or Ag. Metal carrier 70serves as a support member and plating current path for theelectroplating process to form wettable metal contact pads 78 on themetal carrier. Photoresist 76 is removed by a resist stripper.

In FIG. 4 b, semiconductor die 80 and 84 are mounted to contact pads 78on metal carrier 70 with solder bumps 82 and 86, respectively.Alternatively, discrete components or other semiconductor packages canbe attached to contact pads 78. An optional underfill material can beformed below semiconductor die 80 and 84. A molding compound 88 isformed all around semiconductor die 80 and 84 to encapsulate the die,interconnections, and contact pads. Process carrier 72 and adhesive 74are released first, followed by removal of metal carrier 70 by anetching process to expose contact pads 78 as shown in FIG. 4 c.

The interconnect structure is then formed using the steps described inFIGS. 2 d-2 f. More specifically, a first conductive layer like 46 issputtered and patterned, or selectively plated, on a surface of moldedcompound 88 using an adhesion layer, such as Ti. The first conductivelayer electrically connects to contact pads 78 according to theelectrical function and interconnect requirements of semiconductor die80 and 84. A first insulating layer like 51 is formed over moldingcompound 88 and the first conductive layer. The first insulating layercan be made with single or multiple layers of photosensitive polymermaterial or other dielectric material having low cure temperature, e.g.less than 200° C. A portion of the first insulating layer is removed byan etching process to form openings and expose the first conductivelayer. A second conductive layer like 52 is formed over the firstinsulating layer to electrically contact the first conductive layer. Asecond insulating layer like 54 is formed over the first conductivelayer and first insulating layer. The second insulating layer can bemade with single or multiple layers of photosensitive polymer materialor other dielectric material having low cure temperature, e.g. less than200° C. A portion of the second insulating layer is removed by anetching process to form openings and expose the second conductive layer.Solder bumps like 56 can be formed on the exposed second conductivelayer. The first and second conductive layers and first and secondinsulating layers constitute a portion of an interconnect structurewhich routes electrical signals between semiconductor die 80 and 84, aswell as external to the package. Additional insulating layers andconductive layers can be used in the interconnect structure.

FIG. 5 illustrates an embodiment of the semiconductor device. Contactpads 94 are formed using a dummy or sacrificial metal carrier asdescribed in FIG. 2 a. Semiconductor die 90 and 98 are mounted tocontact pads 94 on the metal carrier with wire bonds 96 and 100,respectively. A molding compound 101 is formed all around semiconductordie 90 and 98 to encapsulate the die, wire bonds, and contact pads,similar to FIG. 2 b. The metal carrier is removed by an etching processto expose contact pads 94, in the same manner as described in FIG. 2 c.

A process carrier is applied to a backside of the semiconductor dieusing an adhesive layer to support the package. A conductive layer 102is selectively plated on a surface of molded compound 101 using anadhesion layer, such as Ti. Conductive layer 102 electrically connectsto contact pads 94 according to the electrical function and interconnectrequirements of semiconductor die 90 and 98.

An insulating layer 103 is formed over molding compound 101 andconductive layer 102. The insulating layer 103 can be made with materialhaving dielectric properties. A portion of insulating layer 103 isremoved by an etching process to form openings and expose conductivelayer 102. A conductive layer 104 is formed over insulating layer 103 toelectrically contact conductive layer 102. An insulating layer 106 isformed over conductive layer 104 and insulating layer 103. Theinsulating layer 106 can be made with material having dielectricproperties. A portion of insulating layer 106 is removed by an etchingprocess to form openings and expose conductive layer 104. Conductivelayers 104 and 106 and insulating layers 103 and 106 constitute aportion of an interconnect structure to route electrical signals betweensemiconductor die 90 and 98 as well as external to the package.Additional insulating layers and conductive layers can be used in theinterconnect structure.

An electrically conductive solder material is deposited over conductivelayer 104 through an evaporation, electrolytic plating, electrolessplating, ball drop, or screen printing process. The solder material canbe any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au,Ag, Cu, Bi, and alloys thereof. The solder material is reflowed byheating the conductive material above its melting point to formspherical balls or bumps 108. In some applications, solder bumps 108 arereflowed a second time to improve electrical contact to conductive layer104. An additional under bump metallization can optionally be formedunder solder bumps 108. The interconnections can be solder bumps or bondwires.

FIGS. 6 a-6 b illustrates an embodiment of the semiconductor deviceusing a front-side and backside process carrier. In FIG. 6 a, contactpads 124 are formed using a dummy or sacrificial metal carrier, asdescribed in FIG. 2 a. Semiconductor die 120 and 126 are mounted tocontact pads 124 on the metal carrier with solder bumps 122 and 128,respectively. A molding compound 130 is formed around semiconductor die120 and 126 to encapsulate the die, interconnect, and contact pads,similar to FIG. 2 b. The metal carrier is removed by an etching processto expose contact pads 124, in the same manner as described in FIG. 2 c.

A process carrier is applied to a backside of the semiconductor dieusing an adhesive layer to support the package. A conductive layer 136is selectively plated on a surface of molded compound 130 using anadhesion layer, such as Ti. Conductive layer 136 electrically connectsto contact pads 124 according to the electrical function andinterconnect requirements of semiconductor die 120 and 126.

An insulating layer 138 is formed over molding compound 130 andconductive layer 136. The insulating layer 138 can be made withmaterials having dielectric properties. A portion of insulating layer138 is removed by an etching process to form openings and exposeconductive layer 136. A conductive layer 140 is formed over insulatinglayer 138 to electrically contact conductive layer 136. An insulatinglayer 142 is formed over conductive layer 140 and insulating layer 138.The insulating layer 142 can be made with material having dielectricproperties. A portion of insulating layer 142 is removed by an etchingprocess to form openings and expose conductive layer 140. Conductivelayers 136 and 140 and insulating layers 138 and 142 constitute aportion of a front-side interconnect structure which routes electricalsignals between semiconductor die 120 and 126, as well as external tothe package. Additional insulating layers and conductive layers can beused in the front-side interconnect structure.

A front-side process carrier 146 is mounted to conductive layer 140 andinsulating layer 142 using adhesive layer 144. The adhesive layer 144can be made with thermally or UV light releasable temporary adhesive,typically having a Tg of at least 150° C. The front-side process carriercan be flexible tape or stiff material. The backside process carrier isremoved. Vias are formed through molding compound 130 using laserdrilling or deep reactive ion etch (DRIE). The vias expose contact pads124. Conductive material 148 is deposited in the vias and electricallyconnects to contact pads 124. An insulating layer 150 is formed overconductive layer 148 and molding compound 130. The insulating layer 150can be made with material having dielectric properties. A portion ofinsulating layer 150 is removed by an etching process to form openingsand expose conductive layer 148. Conductive layer 148 and insulatinglayer 150 constitute a portion of a backside interconnect structurewhich routes electrical signals between semiconductor die 120 and 126,as well as external to the package. Additional insulating layers andconductive layers can be used in the backside interconnect structure.

In FIG. 6 b, an electrically conductive solder material is depositedover conductive layer 140 through an evaporation, electrolytic plating,electroless plating, ball drop, or screen printing process. The soldermaterial can be any metal or electrically conductive material, e.g., Sn,Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material isreflowed by heating the conductive material above its melting point toform spherical balls or bumps 152. In some applications, solder bumps152 are reflowed a second time to improve electrical contact toconductive layer 140. An additional under bump metallization canoptionally be formed under solder bumps 152. For the backsideinterconnects, solder bump or wire bond interconnects are formed onconductive layer 148 or the outermost layer.

The semiconductor device in FIG. 7 follows a similar construction asdescribed in FIGS. 6 a-6 b, with the exception that metal pillars 154are formed by selective etching, using contact pads 124 as etching mask.Pillars 154 are made with Cu, Al, or alloys thereof. Metal pillars 154facilitate depositing molded underfill material below semiconductor die120 and 126 due to the elevated interconnect structure. Metal pillars154 further facilitate the formation of vias by laser drilling or DRIEprocess as the via depth can be reduced. The semiconductor deviceexperiences less thermal stress or thermal strain with the higherinterconnection structure.

FIG. 8 shows the semiconductor device of FIG. 7 with contact pads 124and semiconductor die 120 elevated by metal pillars 154. Semiconductordie 158 is mounted to insulating layer 138 with die attach adhesive 160and electrically connected to contact pads 124 and metal pillars 154with wire bonds 162. The die attach adhesive 160 can be made with epoxybased or film based adhesive.

In FIG. 9, the semiconductor device of FIG. 6 b has underfill material164. The underfill material can be made with resin having properTheological and dielectric properties.

In FIG. 10, the semiconductor device of FIG. 6 b has semiconductor die166 physically mounted to and electrically connected through solderbumps 152. Semiconductor die 168 is physically mounted to insulatinglayer 142 with die attach material 170 and electrically connected toconductive layer 140 with wire bonds 172. A molding compound 174 isapplied over semiconductor die 166 and 168 and associated interconnectstructures.

FIG. 11 shows the semiconductor device of FIG. 2 f with process carrier176 and adhesive layer 178 remaining as a heat sink for thermaldissipation or EMI shield.

FIG. 12 shows the semiconductor device of FIG. 2 f with a layer ofphotoresist 180 remaining between contact pads 124.

In summary, the semiconductor device employs a copper sheet as a dummyor sacrificial carrier. A plurality of wettable contact pads ispatterned on the sacrificial carrier. The individual semiconductor dieare mounted to the sacrificial carrier and are electrically connected tothe contact pads. The semiconductor die and contact pads areencapsulated with a molding compound. The sacrificial carrier is removedto expose the metal pads. An interconnect build-up layer is formed onthe contact pads. The wettable contact pads are selectively plated onthe sacrificial metal carrier to provide a highly accurate alignment ofthe bonding pad positions for the electrical interconnect according tothe electrical function of the semiconductor die. By forming contactpads on the sacrificial carrier, a precise placement and alignment forthe later formed requisite interconnect structure can be achieved.Accordingly, the semiconductor package has greater interconnect densityand lower line pitch for individual traces.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A method of making a semiconductor device, comprising: providing afirst sacrificial metal carrier; forming a photoresist layer over thefirst sacrificial metal carrier; forming openings in the photoresistlayer extending to the first sacrificial metal carrier; formingconductive pillars in the openings of the photoresist layer; forming aplurality of contact pads over the conductive pillars, the contact padsbeing selectively electroplated through the openings in the photoresistlayer onto the conductive pillars to provide precise alignment of thecontact pads for electrical interconnect, the conductive pillars andfirst sacrificial metal carrier providing a plating current path forelectroplating the contact pads; removing the photoresist layer;mounting a first semiconductor die to electrically connect to thecontact pads; encapsulating the first semiconductor die, contact pads,and conductive pillars with molding compound; removing the firstsacrificial metal carrier; mounting a second sacrificial carrier over afirst side of the molding compound opposite the contact pads; forming afirst conductive layer over a second side of the molding compoundopposite the first side of the molding compound, the first conductivelayer being electrically connected to the contact pads; forming a firstinsulating layer over the first conductive layer and molding compound;removing a portion of the first insulating layer to expose the firstconductive layer; forming a second conductive layer over the firstconductive layer and first insulating layer; forming a second insulatinglayer over the first insulating layer and second conductive layer;removing a portion of the second insulating layer to expose the secondconductive layer; depositing solder material in electrical contact withthe second conductive layer; reflowing the solder material to form asolder bump; removing the second sacrificial carrier; forming viasthrough the first side of the molding compound to the contact pads, thevias having a reduced depth due to the conductive pillars; forming athird conductive layer over the molding compound and sidewalls of thevias to electrically connect to the contact pads; forming a thirdinsulating layer over the molding compound and third conductive layer,the third insulating layer extending into the vias to cover the thirdconductive layer; and removing a portion of the third insulating layerto expose the third conductive layer.
 2. The method of claim 1, furtherincluding forming a wire bond electrically connected to one of theplurality of contact pads.
 3. The method of claim 1, wherein the firstsemiconductor die electrically connects to the contact pads with solderbumps or wire bonds. 4-5. (canceled)
 6. The method of claim 1, furtherincluding: mounting a second semiconductor die to the solder bump; andencapsulating the second semiconductor die with molding compound. 7.(canceled)
 8. A method of making a semiconductor device, comprising:providing a sacrificial metal carrier; forming a photoresist layer overthe sacrificial metal carrier; forming openings in the photoresist layerextending to the sacrificial metal carrier; forming a plurality ofcontact pads on the sacrificial carrier, the contact pads beingselectively electroplated through the openings in the photoresist layeronto the sacrificial metal carrier to provide precise alignment of thecontact pads for electrical interconnect, the sacrificial metal carrierproviding a plating current path for electroplating the contact pads;removing the photoresist layer; mounting a first semiconductor die toelectrically connect to the contact pads; encapsulating the firstsemiconductor die with molding compound; removing the sacrificial metalcarrier; mounting a second sacrificial carrier over a first side of themolding compound opposite the contact pads; forming a first conductivelayer over a second side of the molding compound opposite the first sideof the molding compound, the first conductive layer being electricallyconnected to the contact pads; forming a first insulating layer over thefirst conductive layer; removing the second sacrificial carrier; formingvias through the first side of the molding compound to the contact pads;forming a second conductive layer over the molding compound and into thevias to electrically connect to the contact pads; and forming a secondinsulating layer over the molding compound and second conductive layer9. The method of claim 8, further including: depositing solder materialon the first conductive layer; and reflowing the solder material to forma solder bump.
 10. The method of claim 9, further including: mounting asecond semiconductor die to the solder bump; and encapsulating thesecond semiconductor die with molding compound.
 11. (canceled)
 12. Themethod of claim 8, wherein the first semiconductor die electricallyconnects to the contact pads with solder bumps or wire bonds. 13-15.(canceled)
 16. A method of making a semiconductor package, comprising:providing a sacrificial metal carrier; forming a photoresist layer overthe sacrificial metal carrier; forming openings in the photoresist layerextending to the sacrificial metal carrier; forming a plurality ofcontact pads on the sacrificial carrier, the contact pads beingselectively electroplated through the openings in the photoresist layeronto the sacrificial metal carrier to provide precise alignment of thecontact pads for electrical interconnect, the sacrificial metal carrierproviding a plating current path for electroplating the contact pads;mounting a first semiconductor die to electrically connect to thecontact pads; encapsulating the first semiconductor die with moldingcompound; and forming an interconnect structure over the moldingcompound and electrically connected to the contact pads.
 17. The methodof claim 16, wherein forming the interconnect structure includes:forming a first conductive layer over the molding compound andelectrically connected to the contact pads; forming a first insulatinglayer over the first conductive layer; and removing a portion of thefirst insulating layer to expose the first conductive layer.
 18. Themethod of claim 17, further including: forming a second conductive layerover the first insulating layer and electrically connected to the firstconductive layer; forming a second insulating layer over the secondconductive layer; and removing a portion of the second insulating layerto expose the second conductive layer.
 19. The method of claim 18,further including mounting a front-side process carrier to the secondinsulating layer with an adhesive layer.
 20. The method of claim 19,further including: forming vias through the molding compound to thecontact pads; forming a second conductive layer in the vias toelectrically connect to the contact pads; forming a second insulatinglayer over the second conductive layer; and removing a portion of thesecond insulating layer to expose the second conductive layer.
 21. Themethod of claim 17, further including: depositing solder material on thefirst conductive layer; and reflowing the solder material to form asolder bump.
 22. The method of claim 16, further including removing thesacrificial carrier.
 23. The method of claim 16, wherein the firstsemiconductor die electrically connects to the contact pads with solderbumps or wire bonds.
 24. The method of claim 16, further includingforming a pillar under each of the plurality of contact pads.